module fmul(
    input  [31:0] a,
    input  [31:0] b,
    input  [1:0] rm,
    output [31:0] s
);

logic a_expo_is_00 = ~|a[30:23]; // exponential field is 00
logic b_expo_is_00 = ~|b[30:23];
logic a_expo_is_ff =  &a[30:23]; // exponential field is ff
logic b_expo_is_ff =  &b[30:23];
logic a_frac_is_00 = ~|a[22:0]; // exponential field is 00
logic b_frac_is_00 = ~|b[22:0];

logic a_is_inf = a_expo_is_ff & a_frac_is_00; 
logic b_is_inf = b_expo_is_ff & b_frac_is_00; 
logic a_is_nan = a_expo_is_ff & ~a_frac_is_00;
logic b_is_nan = b_expo_is_ff & ~b_frac_is_00;
logic a_is_0   = a_expo_is_00 & a_frac_is_00;
logic b_is_0   = b_expo_is_00 & b_frac_is_00;

logic is_inf_nan = a_is_inf | b_is_inf | a_is_nan | b_is_nan;
logic s_is_nan = a_is_nan | (a_is_inf & b_is_0) | b_is_nan | (a_is_0 & b_is_nan);
logic [22:0] nan_frac = ({1'b0, a[22:0]} > {1'b0, b[22:0]}) ? {1'b1, a[21:0]} : {1'b1, b[21:0]};
logic [22:0] inf_nan_frac = s_is_nan ? nan_frac : 23'd0;

logic sign = a[31] ^ b[31];
logic [22:0] exp10 = {2'b0, a[30:23]} + {2'b0, b[30:23]} - 7'd127 + a_expo_is_00 + b_expo_is_00;

wire [23:0] a_frac24 = {~a_expo_is_00, a[22:0]};
wire [23:0] b_frac24 = {~b_expo_is_00, b[22:0]};
wire [47:0] z;
wire [38:0] z_sum;
wire [39:0] z_carray;
wallace_tree


endmodule